1. Field of the Invention
Embodiments of the invention relate to control methods for multilevel power conversion circuits using flying capacitors for AC motor drive.
2. Description of the Related Art
FIG. 14 shows an example of a seven-level inverter circuit, a multilevel power conversion circuit for converting a DC power to an AC power. A DC power supply system with a voltage of 3 Ed×2 consisting of series-connected DC power supplies of DP1 and DP2 has a positive potential terminal P, a negative potential terminal N, and a middle potential terminal M. The DC power supply system can be constructed with an AC power supply system generally using double series connection of rectifiers and large capacity capacitors (not shown in the figure). Semiconductor switches, which are six IGBTs S1 through S6 with antiparallel-connected diodes, are connected in series between the positive potential terminal P and the negative potential terminal N of the DC power supply system. Other semiconductor switches, which are four IGBTs S7 through S10 with antiparallel-connected diodes, are connected in series between the connection point of the IGBT 51 and the IGBT S2 and the connection point of the IGBT S5 and the IGBT S6. An antiparallel-connected circuit of bidirectional semiconductor switches consisting of an IGBT S11 and IGBT S12 is connected between the middle potential terminal M of the DC power supply system and the connection point of the IGBT 8 and the IGBT 9.
The bidirectional semiconductor switch can be composed by anti-parallel connection of reverse-blocking IGBTs as shown in FIG. 14, or alternatively, by combinations of an IGBT without reverse-blocking ability and a diode as shown in FIGS. 15A, 15B, and 15C. Capacitors C1a, C1b, and C2 are so-called flying capacitors and controlled at an average voltage across each capacitor of: Ed for the capacitor C1a, 2Ed for the capacitor C2, and Ed for the capacitor C1b for the case of the voltage of the DC power supply system of 3Ed×2. By means of the voltage supplied by the DC power supplies DP1 and DP2 and charging and discharging process of these capacitors, multilevel voltages between 3Ed and −3Ed at an interval of one Ed are delivered at an AC terminal ACT. Thus, the converter of this circuit construction is a seven-level output inverter that delivers at the AC terminal ACT seven output potentials of P, P−Ed, P−2Ed, 0, N+2Ed, N+Ed, and N by means of ON/OFF operation of the semiconductor switches of the IGBTs and voltages across the three capacitors C1a, C1b, and C2. The circuits described above is a one phase portion AU of a three phase inverter as shown in FIG. 16 composed of three phase-portions of AU, AV, and AW. An AC motor ACM is a load on this power conversion system. FIG. 21 shows a circuit example using semiconductor switches with equal withstand voltages. The series-connected IGBTs S1a through S1d in FIG. 21 correspond to the IGBT S1 in FIG. 14 and the series-connected IGBTs S6a through S6d in FIG. 21 correspond to the IGBT S6 in FIG. 14.
FIG. 18 shows an example of waveform of the output line voltage Vout in PWM control of the seven level inverter of FIG. 21 or FIG. 14. This power conversion system with a one step of voltage change of Ed delivers an output voltage waveform nearer to the sinusoidal waveform as compared with a two level type inverter, thus generating fewer harmonics at low order and reducing switching loss in the semiconductor switches. Therefore, a high efficiency power conversion system can be constructed.
FIG. 17 shows a basic circuit of a multilevel conversion circuit. This circuit is disclosed in a Japanese Translation of PCT International Application No. 2009-525717 (also referred to herein as “Patent Document 1”) and comprises IGBTs Q1 through Q6 and a capacitor Cf. Some conversion circuits can be added to the terminals TA and TB to construct a multilevel conversion system.
The seven level inverter circuit of FIG. 14 as described above can deliver seven levels of output potentials: 3 Ed, 2Ed, Ed, 0, −Ed, −2Ed, and −3Ed. The inverter circuit is controlled by performing PWM control and changing-over these seven levels of potentials to deliver voltage similar to the sinusoidal waveform. Here, a step of voltage change generated by the changeover of a switching pattern is preferably Ed in view of breakdown in the motor side. Although a changeover pattern is possible to generate a step of voltage change of 2Ed or 3Ed, such a change-over pattern is normally not carried out for this reason. Thus, the potential at the AC terminal ACT during PWM control changes in transition between the next level of potential in the series of 3Ed−2Ed−Ed−0−(−Ed)−(−2Ed)−(−3Ed).
To avoid complexity in control, in the process of potential change of Ed→0→−Ed at the AC terminal ACT, the zero voltage output pattern in the transition from Ed to zero potential is restricted to the pattern shown in FIG. 19 in which the switches S12, S11, S9, S10, S5, and S4 are in the ON state. The current can flow in the opposite direction depending on the power factor of the load. Similarly, in the process of potential change of −Ed→0→+Ed at the AC terminal ACT, the zero voltage output pattern in the transition from −Ed to zero potential is restricted to the pattern shown in FIG. 20 in which the switches S3, S2, S7, S8, S11, and S12 are in the ON state. The current can flow in the opposite direction depending on the power factor of the load.
In the seven-level inverter circuit of FIG. 14, there are five switching patterns (1) through (5) shown below that deliver an output voltage of −Ed at the AC terminal ACT. Likewise, there are five patterns that deliver an output voltage of +Ed.
(1) S2, S3, S6, S7, S8, and S11 are in the ON state.
(2) S4, S5, S8, S10, S11, and S12 are in the ON state.
(3) S2, S4, S7, S8, S11, and S12 are in the ON state.
(4) S4, S5, S7, S9, S11, and S12 are in the ON state.
(5) S3, S5, S7, S8, S11, and S12 are in the ON state.
Switching patterns that deliver an output voltage of −2Ed are following three patterns (1), (2), and (3). Likewise, there are three patterns that deliver an output voltage of 2Ed.
(1) S3, S5, S6, S7, S8, and S11 are in the ON state.
(2) S2, S4, S6, S7, S8, and S11 are in the ON state.
(3) S4, S5, S7, S8, S11, and S12 are in the ON state.
Switching pattern that delivers an output voltage of −3Ed is the following one pattern (1). Likewise, there is one pattern that delivers an output voltage of 3Ed.
(1) S4, S5, S6, S7, S8, and S11 are in the ON state.
Of these switching patterns, the two patterns (2) and (4) in the five patterns that deliver an output voltage of −Ed use the capacitor C1a. Two more patterns that deliver the output voltage of Ed actually use the capacitor C1a summing up to total of four patterns.
Since the PWM control may output the same switching pattern in at least one carrier period, a capacity of the flying capacitors needs to be designed based on the three parameters of: the range of permitted voltage variation of the capacitor, the integrated current flowing in the capacitor, and the carrier period.
The capacitance needed by a flying capacitor is large in a capacitor with a narrow range of permitted voltage variation, in a capacitor carrying a large current, and in a capacitor with a long carrier period. Since a system using a multilevel inverter generally handles a high voltage of several kilovolts, a capacitor used there should be a film capacitor or an oil capacitor having a large volume, which causes a high cost. Thus, as can be seen from the above discussion, there is a need in the art for an improved control method for a multilevel power conversion circuit.